Dear all,

Please find the details/steps for Registration of NPTEL Exams for all RGUKT students including Free Elective Students (Pay Via SPOC).

Last Date for Registration is Feb 12th 5 pm, Please Start Registering from Today Onwards to avoid Overload on NPTEL Site.

All E4 Free Elective Students must Complete Exam Registration Soon.

The Detailed Steps and all necessary information is provided in the attachment. (Pay via SPOC)

After Registration, Please Pay Fee on the same day and who register and do not pay fee, there names would not be considered and they have to do Direct Payment

In case of any queries, Please get back to Mr. S.C.Rakesh Roshan, NPTEL SWAYAM Coordinator, RGUKT Basar

Download: Notice Attachment

Dear Student,

                                Job Description for Software Developer

Darwinbox ( www.darwinbox.in ) is an HR Technology firm with a vision to springboard companies
to the next stage of digital evolution. It has been founded by IIT/IIM/XLRI grads with experience in
companies like McKinsey, Deloitte, EY, Google across the sectors in multiple disciplines of management and technology.

Darwinbox HR in a new age integrated HR platform to engage and empower employees on one
side while automating and simplifying all HR processes
We launched Darwinbox HR in the market and it has received strong positive feedback. We have
onboarded some marquee clients and are looking to scale up our team to build more innovative
features and ensure best experience for our clients.
We are based out of Hyderabad

What’s in for you?
You will be one of members of the founding employee group playing a pivotal role building the
coolest next generation enterprise products. We promise you best-in industry compensation.
More importantly, we will provide you challenging yet fun filled working environment, exposure to
complete product development lifecycle, real time business challenges and how you are going to
address them through digital products. You will also have a chance to work with and be mentored
by the founders directly

Software Developer at Darwinbox - What do we look for?:

As fitment with the organization culture is very important, you will immensely like the job if you
▪ enjoy working in a fast paced company environment
▪ like to see business impact of whatever they do for the customer
▪ prefer non-hierarchical, independent and non-pushy environment
▪ are self-motivated to take up high degree of ownership

Last Date for Registration: 2nd Feb 2017,2:00PM

Download: Notice Attachment

Dear Students,

Please find the enclosed subject cited above.


Sd/-
Academic Section.

Download: Notice Attachment

Registration Open for  MosChip Technologies Recruitment Drive
Dear Students,
We are pleased to announce the MosChip Recruitment Drive for Graduates of the 2025 batch.

Embedded and Digital fresher hiring for 2025 
Job Description I:  Read Here
Recruitment for Core SW - ESW & SW Design

MosChip is looking for BE/BTech Final Year Students (going to be passed out) with Electronics or Computer Science as one major stream (ex: CSE, ECE, EEE, EIE Branches) for our requirement to Embedded Software and Software Product Design Teams. Selected students will work on the development of Embedded Software or Product Software which is a dream job for many Computer Science Engineers. The minimum eligibility criteria for writing the examination are that the student must have obtained an overall percentage of minimum 60% marks till now. 

The Selection Process follows Three Steps as described below. 

Step1: Preliminary Examination (Online), An objective type of online examination for 90-minute duration consisting of questions from Aptitude, Processors and Programming domains. The exam must be conducted at the College premises. The students who clear the Preliminary Examination will be called for writing the Main Examination.

Step2: Main Examination (Physical Paper), The Main examination consists of two papers (Embedded SW and Programming) that must be answered by all Students. The Embedded SW section paper is for 90 minutes duration and Programming Section paper for 90 Minutes duration. Students who clear the Main Examination will be called for interview to finalize selection. 

Step3: Interview. The interview is to find out the technical passion of the student. It will be a day long interview to check candidates’ skill and interest in ESW and Programming domains. The idea of the interview is to hand hold and guide students in discovering their area of interest and passion. 

 
ESW Design – Salary Range: 4-6 Lakhs - Job Description:
Candidates will have the opportunity to design the embedded software for various types of Boards that are made to test different applications. Typically, they may work on the following types of applications    
    
•	Video and Audio Processing Boards
•	AI/ Edge related Applications
•	Simple embedded applications for commercial use
•	Various development boards for ASICs
•	Various evaluations boards for ASICs
•	Embedded boards for Auto industry applications
•	Industrial sector based embedded applications


Software Product Design – Salary Range: 4-6 Lakhs - Job Description:
Candidates will have the opportunity to design Software Products based on Standards. Typically, they may work on the following product applications    
    
•	DLMS Stack Development
•	WiFi/USB/Bluetooth/PCIe like Protocol Software
•	Application Software for simple embedded applications
•	App development on Mobiles
All Selected students who wish to join must abide by 
1.	Will undergo 6 months training at MISS in their respective domain
2.	Every Student must sign a bond for 4 ½ years including training period to serve the company
3.	Any student who wishes to break the bond before a 4 ½ year term must pay 8 Lakhs 
4.	Salary will be decided based on performance during Training

Job Description II:  Read Here

Recruitment for Core Electronics - VLSI Analog Design & Digital Design

MosChip is looking for BE/BTech Final Year Students (going to be passed out) with Electronics as one major stream (ex: ECE, EEE, EIE Branches) for our requirement to Analog Design and Digital Design Teams. Selected students will work on product (ASIC) and IP development, which is a dream job for many Electronics Engineers. The minimum eligibility criteria for writing the examination are that the student must have obtained an overall percentage of minimum 60% marks till now. 

The Selection Process follows Three Steps as described below. 

Step1: Preliminary Examination (Online), An objective type of online examination for 90-minute duration consisting of questions from Aptitude, Analog and Digital domains. The exam must be conducted at the College premises. The students who clear the Preliminary Examination will be called for writing the Main Examination.

Step2: Main Examination (Physical Paper), The Main examination consists of two papers (Analog and Digital) that must be answered by all Students. The Analog section paper is for 90 minutes duration and Digital Section paper for 90 Minutes duration. Students who clear the Main Examination will be called for interview to finalize selection. 

Step3: Interview. The interview is to find out the technical passion of the student. It will be a day long interview to check candidates’ skill and interest in Analog and Digital domains. The idea of the interview is to hand hold and guide students in discovering their area of interest and passion. 

 
Analog Design – Salary Range: 6-8 Lakhs - Job Description:
Candidates will have the opportunity to design varieties of analog design blocks based on the products they work for in the Company. Candidates will get an opportunity to work on multiple technologies, across multiple Foundries like TSMC 4nm/5nm/12nm/22nm/65nm/90nm/180nm, GF 22FDX/12nm/40nm, etc... Typically, they may work on the following Blocks    
    
•	Analog-to-digital converters (ADC)   
•	Digital-to-analog converters (DAC)   
•	Phase-Locked Loop (PLL), DPLL 
•	Serializer, De-serializer (Serdes)   
•	Clock and data recovery (CDR) circuits   
•	Comparators, Threshold detectors
•	Regulators, Power Management Circuits
•	BGR, Bias Generators, Switching Circuits, Amplifiers


Digital Design – Salary Range: 4-6 Lakhs - Job Description:
Candidates will have the opportunity to design varieties of Digital design blocks based on the products they work for in the Company. Candidates will get an opportunity to work on multiple technologies, across multiple Foundries like TSMC 4nm/5nm/12nm/22nm/65nm/90nm/180nm, GF 22FDX/12nm/40nm, etc... Typically, they may work on the following Blocks    
    
•	Industry Standard Protocol Based Designs
•	Digital Designs that need to work with Microprocessors
•	Algorithm Implementations
•	Filters Designs
•	Computation Designs
•	SoC Related Designs
•	Building Design Verification Environment
•	Designing BFMs, Checkers, Models etc..

All Selected students who wish to join must abide by 
1.	Will undergo 6 months training at MISS in their respective domain
2.	Every Student must sign a bond for 4 ½ years including training period to serve the company
3.	Any student who wishes to break the bond before a 4 ½ year term must pay 8 Lakhs for Digital and 10 Lakhs for Analog Domain 
4.	Salary will be decided based on performance during Training

How to Apply:
Interested and eligible students can apply through the following link: Apply Here https://forms.gle/pDz3TuAEj4Etzehq6


⏳ Deadline: April 25, 2025.

Training & Placement Office
RGUKT-Basar

Download: Notice Attachment

Dear Students

Please find the attachment of the subject cited.

Sd/-
Academic Section

Download: Notice Attachment

Dear student,

FINAL LIST OF XENOVUS SOFTWARE SOLUTIONS

                           SELECTION PROCESS:

1.	Pre-placement talk
2.	Online written test
3.	Personal interview for shortlisted students.

sd/-
placement office

Download: Notice Attachment

The following students are not registered for PUC-I SEM2.
You are required to report Academic section immediately.
AY 19-20 PUC-I sem2 Not Registered students list as on 18.12.19
S.No	Id No.	Student Name	Gender	Class room
1	B191702	RAMELLI SAMATHA	F	K-5
2	B192214	AMTUL SUBOOR	F	λ-1
3	B192507	KUNKUMA VAISHNAVI	F	λ-1
4	B192360	BURKA JAHNAVI	F	λ-3
5	B192509	VEMULA VAISHNAVI	F	λ-9
6	B191155	MALYALA SRAVANI	F	ω-3
7	B192576	APPALA AKSHAYA BHARATHI	F	Ф-1
8	B192658	THURAI SIMAN	M	Ф-1
9	B191239	REDDIMALLA GOWTHAMI	F	Ф-2
10	B192495	KALA DEEPIKA	F	Ф-3
11	B192644	VANARASI KALYANI	F	Ф-5
12	B191877	VADNALA SAI CHARAN	M	Ф-6
13	B192681	KOPPULA PRAVALIKA	F	Ф-7

Sd/-
Academic Section

Kindly find detials about the same:

Job Role: LAB ENGINEER
Job Location: Bangalore
CTC: 6.8 Lakhs/annum

Educational Qualifications:
·         Diploma(Electrical/Electronics/Mechatronics) (2017 and 2018)
·         BSC(Electronics)
Interview Locations:
·         Bangalore
·         Hyderabad
·         Chennai
·         Cochin
·         Mumbai
·         Pune

For more details and to apply click on below URL.

URL: https://www.firstnaukri.com/careers/customised/landingpage/texas/index.html
Last Date to Apply: 31st March 2018

 

Dear Students,
     Please find attached schedule of the AY23 -24 E4_ME_ Sem 2_mid - Sem major project presentation.

Regards,
Head,
M.E. Department

Download: Notice Attachment

Dear Students,
find the attachment for the subject cited above.

Sd/-
Academic Section

Download: Notice Attachment

Dear All,

Please find the AY21-22, E1_Sem- I, Mechanical Engineering -Updated Timetable as on 25.02.2022


Sd/-
Academic Section

Download: Notice Attachment

Dear student,

All shortlisted students need to report to New Placement Office for interviews by 4:30 PM along with resume and all certificates.



sd/-
Placement Office

Download: Notice Attachment

It is hereby informed to all the E-4 CRs (Class Representatives) are instructed to attend a meeting at Scholarship Section in Administrative Block, today (i.e., 01.11.2018) at 03.00PM.

Dear Students,

                P2S1 & P2S2 Rem-remedial examinations for 2014 batch will be held from 16/07/2016. Detailed time table will be displayed soon.

Dear students,

Go through the attached JD of RIVIGO Prime.



sd/-
Placement Office.

Download: Notice Attachment

Dear PUC-II students,

It is to inform that all the PUC-II students are allotted the classes at Old Block tentatively from 19.06.2017. Hence, I inform you to sit in the previous classes i.e. PUC-I.

Regards,

Academic Section

Dear Student,

Please find enclosed the AY19-20 Academic Calendar. This is for your information.

Sd/-
Associate Dean of Sciences and Humanities
Associate Dean of Engineering.

Download: Notice Attachment

Dear students 
Please find the file attached here with for the Lab Remedial Examinations conducted by Department of CSE.

Download: Notice Attachment